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Fraunhofer IESE Partners With Arteris To Accelerate Advanced Network-on-chip Architecture Development for AI/ML Applications

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Arteris and Fraunhofer IESE partner to enable interoperability between their respective technologies for advanced DRAM-centric NoC development.
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Combining FlexNoC and Ncore from Arteris with Fraunhofer IESE DRAMSys4.0 enables customers to improve performance, reduce cost and accelerate the advanced DRAM-centric SoC development schedules

CAMPBELL, Calif., Oct. 17, 2023 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation and Fraunhofer IESE, one of the leading research institutes in the area of software and systems engineering methods, today announced they have partnered to enable interoperability between Arteris' FlexNoC and Ncore network-on-chip (NoC) development environment and Fraunhofer IESE's DRAM subsystem design space exploration framework. The interoperability will improve performance, reduce cost and accelerate the schedule of advanced DRAM-centric NoC development for mutual customers.

"Early, accurate modeling of the characteristics of the latest DRAM architectures is a critical component to arrive at optimal power-optimized SoC architectures," said Professor Dr. Matthias Jung, an expert in virtual engineering at Fraunhofer IESE. "By enabling interoperability and integration between Arteris' FlexNoC and Ncore with DRAMSys4.0, our customers can understand the impact of advanced DRAM technology on NoC performance and power consumption at the earliest project stages, avoiding surprises leading to architecture redesigns later in the project cycle."

DRAM performance is critical for today's advanced AI/ML architectures due to requirements on efficiency of data movement, computation, AI model complexity, real-time inference and energy consumption. While models of memory controllers impact memory access mapping, command generation and timing control, memory organization, configuration and error correction, memory models also manage data storage, access, retrieval, refresh and retention. DRAMSys consists of models that reflect the DRAM functionality, power, and temperature. It allows system designers to analyze the limiting parameters and issues concerning current DRAM standards in the context of system and NoC architectures. The interoperability between Arteris and Fraunhofer IESE technology enables designers to complete a thorough performance analysis in the context of DRAM architectures before committing to a NoC architecture.

"Generative AI SoCs have memory-centric architectures. The performance and flexibility of Arteris interconnect IP products support ultra-high bandwidth traffic to feed data to advanced memory architectures supported by the Fraunhofer IESE memory exploration framework," said Frank Schirrmeister, vice president solutions and business development at Arteris. "Together, we can enable our customers to reduce cost and schedules for their highly differentiated and performance-optimized NoC architectures."

"We are more than happy that this project, which started as a research endeavor at RPTU Kaiserslautern-Landau, was further developed with Fraunhofer IESE into a tool that is now used in the industry," said Professor Dr. Norbert Wehn from the RPTU University of Kaiserslautern-Landau. “This collaboration is a positive step forward for designers everywhere.”

The integration of Arteris and Fraunhofer offerings is available today. For more information contact info@arteris.com and anfrage@iese.fraunhofer.de.

About Arteris

Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com.

About Fraunhofer IESE

The Fraunhofer Institute for Experimental Software Engineering IESE in Kaiserslautern has been one of the leading research institutes in the area of software and systems engineering as well as innovation engineering for over 25 years. With its applied research, the institute develops innovative solutions for the design of dependable digital ecosystems, thereby accelerating the economic and social benefits for its customers. Fraunhofer IESE provides support in mastering challenges in a wide variety of application areas, with particular expertise in the areas of “EDA-Software” and “Digital Twin / Virtual Engineering” Fraunhofer IESE is one of 76 institutes and research units of the Fraunhofer-Gesellschaft. Together they have a major impact on shaping applied research in Europe and worldwide and contribute to Germany’s competitiveness in international markets.

© 2004-2023 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.


What is the partnership between Arteris and Fraunhofer IESE about?

The partnership aims to enable interoperability between Arteris' FlexNoC and Ncore network-on-chip (NoC) development environment and Fraunhofer IESE's DRAM subsystem design space exploration framework.

How will the partnership benefit customers?

The partnership will improve performance, reduce cost, and accelerate the schedule of advanced DRAM-centric NoC development for mutual customers.

Why is DRAM performance critical for AI/ML architectures?

DRAM performance is critical for AI/ML architectures due to requirements on efficiency of data movement, computation, AI model complexity, real-time inference, and energy consumption.

What does DRAMSys consist of?

DRAMSys consists of models that reflect the DRAM functionality, power, and temperature.

What does the integration of Arteris and Fraunhofer offerings enable?

The integration enables designers to complete a thorough performance analysis in the context of DRAM architectures before committing to a NoC architecture.
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arterisip provides network-on-chip interconnect ip to soc makers so they can reduce cycle time, increase margins, and easily add functionality. unlike traditional solutions, arteris’ plug-and-play technology is flexible and efficient, allowing designers to optimize for throughput, power, latency and floorplan. using arterisip solves pain for our customers. traditional bus and crossbar interconnect approaches create serious problems for architects, digital and physical designers, and integrators: massive numbers of wires, increased heat and power consumption, failed timing closure, spaghetti-like routing congestion leading to increased die area, and difficulty making changes for derivatives. arterisip noc ip reduces the number of wires down to one half, results in fewer gates, fewer and shorter wires, and a more compact chip floor plan. having the option to configure each connection’s width, and each transaction’s dynamic priority assures meeting latency and bandwidth requirements. and